As biological wide-field visual neurons in locusts, lobula giant motion detectors (LGMDs) can effectively predict collisions and trigger avoidance before the collision occurs. This capability has extensive potential applications in the field of autonomous driving, unmanned aerial vehicles, and more. Currently, describing the LGMD characteristics is divided into two viewpoints, one emphasizing the presynaptic visual pathway and the other emphasizing the postsynaptic LGMDs neuron. Indeed, both have their research support leading to the emergence of two computational models, but both lack a biophysical description of the behavior in the individual LGMD neuron. This paper aims to mimic and explain LGMD's individual behavior based on fractional spiking neurons and construct a biomimetic visual model for the LGMD compatible with these two characteristics. Methods: We implement the visual model in the form of spikes by choosing an event camera rather than a conventional CMOS camera to simulate the photoreceptors and follow the topology of the ON/OFF visual pathway, enabling it to incorporate the lateral inhibition to mimic the LGMD's system from the bottom up. Second, most computational models of motion perception use only the dendrites within the LGMD neurons as the ideal pathway for linear summation, ignoring dendritic effects inducing neuronal properties. Thus, we introduced fractional spiking neuron (FSN) circuits into the model by altering dendritic morphological parameters to simulate multiscale spike frequency adaptation (SFA) observed in LGMDs. In addition, we have attempted to add one more circuit of dendritic trees into fractional spiking neurons to be compatible with the postsynaptic FFI in LGMDs and provide a novel explanatory approach and a predictive model for studying LGMD neurons. Results: Finally, we test that the event-driven biomimetic visual model can achieve collision detection and looming selection in different complex scenes, especially fast-moving objects.
Electronic parts in space inevitably subject to radiation effects leading to the degradation of electronic performance or even failure, so radiation performance of an electronic part must be assessed to ensure it work normally in space. At present, to assess the ion radiation effects on a semiconductor device is directly through irradiation tests. However, due to the scarcity of cyclotron resources, the test time is difficult to appoint and the cost is huge. Due to schedule and budget constraints, it is also impossible to conduct irradiation tests on all semiconductor devices in actual space missions. Therefore, assessment of the radiation effects on semiconductor devices through irradiation tests has caused difficulties. Radiation susceptibility of semiconductor device is determined by the design topology and fabrication technology, and the irradiation test data shows that similar semiconductor devices has similar radiation susceptibility, so a method to assess the radiation effects on semiconductor devices base on similarity theory is proposed at first time in this paper. This assessing method does not require irradiation testing and does not require separate sampling. It has the virtues of easy implementation, quick response and low cost, providing an efficient method of assessing radiation effects on semiconductor devices.
Switched-capacitor converters (SCCs) are subset of switched-mode converters which can be designed to buck/boost the input voltage. However, synthesizing SCC has been a challenging task due to the large number of possible circuit realizations. This work proposes a synthesis method for constructing an efficient reconfigurable SCC that adheres to the Fibonacci canonical structure. The optimization is achieved by operating the converter with the minimum number of capacitors required to achieve a certain voltage conversion ratio (VCR). Indeed, decreasing the number of flying capacitors minimizes the equivalent output resistance of the converter which improves the converter performance, like the settling time and the power conversion efficiency (PCE). Moreover, by analyzing the differences between each VCR terminal, the number of switches required to create a unique VCR is also decreased. The performance of the proposed synthesis tool is verified using SPICE simulations for 4-stage reconfigurable SCC. The simulated converter efficiency ranges from 85% to 95% for a 50mA load tested at 1 MHz switching frequency, compared to 43.5% to 86% using the conventional method. The performance of the converter is compared with recent reconfigruable SCCs in the literature.
This work delves into the exploration of optimizing Multilayer Perceptrons (MLP) or the dense layers of other sorts of Deep Neural Networks when they are aimed at edge computing applications such as Internet of Things (IoT) devices, very limited in resources at the edge. The proposed optimization approach consists of generating a pruning mask for the hidden dense layers of the original neural network by using auxiliary dense Morphological Neural Networks (MNN). These MNN have shown a notable efficiency when it comes to the process of pruning, resulting in a significant decrease in the overall number of connections and a low cost in terms of accuracy degradation. The effectiveness of this new pruning methodology has been explained in detail and validated for two widely used datasets as MNIST and Fashion MNIST and two very well-known neural networks such as LeNet-5 and LeNet-300-100. Subsequently, the performance of these pruned neural networks has been assessed using an IoT hardware platform. The experimental results have outperformed other contemporary state-of-the-art pruning techniques, in terms of power efficiency and processing speed for a similar percentage of weight reduction, all while maintaining minimal impact on overall accuracy. In addition, a custom software tool has been developed to generate a C code designed to optimize the inference of these pruned networks on IoT edge devices. These findings hold important implications for advancing the development of efficient and scalable deep learning models that are specifically tailored to meet the demands of edge computing applications.
We are designing and implementing a solar inverter system that generates green power from solar energy and reduces air pollution and other environmental impacts. Our system uses a pure sine wave inverter that produces a sine wave virtually identical to the utility grid. The IoT-based MPPT solar charge controller ensures that the maximum amount of power is transferred from the solar panels to the battery bank and monitors the system in real-time. We also use a solar tracker with a single-axis rotation that orients the panels toward the sun in two directions. Our solar inverter system can handle a maximum load of 300 watts.
In this study, we present an analytical model for predicting the magnetic properties and optimization of thermomagnetic devices using mathematical models. The 3D analytical magnetic model is firstly validated by the dipole model and confirmed through experimentation, enabling to accurately estimate the magnetization of the used magnet. The stray field induced by the permanent magnet over the lateral surface of the rotor is computed. Then, the resultant force and torque are derived allowing to estimate the exact number of ferromagnetic active material required and their angular gap.
In this study, novel Lorentz-like fractional-order dynamical systems are proposed, offering potential applications across various engineering domains. Based on a threedimensional system of the Lorentz-like type of integer order, new nonlinear dynamic systems of fractional order are constructed for four, five, and six state variables. These systems can describe real convective processes in fractal media characterized by a memory effect. For these systems, equilibrium points and stability conditions are determined using the theorem on local asymptotic stability of fractional order systems. Utilizing the frequency domain approximation method, Matlab-Simulink models were developed for novel chaos generators characterized by a fractional order index of 0.95. Through the utilization of Multisim software, we designed electronic circuits to validate the physical feasibility of our proposed systems. The simulation results obtained from both Matlab and Multisim exhibit excellent agreement, reinforcing the reliability of our proposed models. To demonstrate the synchronization of two unidirectionally coupled 3.8d chaotic systems, Matlab-Simulink models were created in two versions. The first version assumes an identical fractional index for both the master and slave systems, while the second version involves different fractional indices for the two systems. These systems were further employed for the chaotic masking of a harmonic signal. An electronic circuit implementing the chaotic masking process in Multisim is also presented. The results obtained from this proposed scheme demonstrate the success of the approach in accomplishing the encryption and decryption procedures effectively.
In this work, we propose a model that describes the temporal evolution of the threshold voltage and trapped charge density in Thin-Film Transistors (TFTs) under dynamic conditions, paving the way for the characterization of memory transistors. The model is expressed as a first order differential equation for the trapped charge density, which is controlled by a time constant and an independent term proportional to the drain current. The time dependent threshold voltage is introduced in a previously developed compact model for TFTs with special consideration to the contact effects. The combination of both models and the use of an evolutionary parameter extraction procedure allow for reproducing the experimental dynamic behavior of TFTs. The results of the model and the evolutionary procedure have been validated with published experimental data of pentacene-based transistors. The procedure is able to simultaneously reproduce three kinds of experiments with different initialization routines and constraints in each of them: output and transfer characteristics with hysteresis and current transients characteristics.
Stringent physical requirements need to be met for the high performing surface-electrode ion traps used in quantum computing, sensing, and timekeeping. In particular, these traps must survive a high temperature environment for vacuum chamber preparation and support high voltage rf on closely spaced electrodes. Due to the use of gold wirebonds on aluminum pads, intermetallic growth can lead to wirebond failure via breakage or high resistance, limiting the lifetime of a trap assembly to a single multi-day bake at 200 • C. Using traditional thick metal stacks to prevent intermetallic growth, however, can result in trap failure due to rf breakdown events. Through high temperature experiments we conclude that an ideal metal stack for ion traps is Ti20nm/Pt100nm/Au250nm which allows for a bakeable time of roughly 86 days without compromising the trap voltage performance. This increase in the bakable lifetime of ion traps will remove the need to discard otherwise functional ion traps when vacuum hardware is upgraded, which will greatly benefit ion trap experiments.
This paper describes a method for automatically transforming the structure and characteristics of an image processing dataflow graph for the purpose of improving performance and/or lowering memory utilization as compared to the baseline tools. Embedded image processing applications are often executed on Digital Signal Processors, or their modern equivalent Visual Processor Units. The software usually performs a series of pixel-level operations for basic color conversion, channel extraction and combining, arithmetic, and filtering. These steps can often be efficiently described as a graph. For this reason, standard libraries such as OpenVX are used, which provide a graph-based programming model where the nodes are chosen from a repertoire of common pixel-level operations and the edges represent the flow of images as they progress though the processing stages. Generally speaking, each node is processed sequentially in the order implied by the data dependencies defined by the graph structure, with all intermediate values stored in external memory. In the proposed framework, we developed performance models for both the direct memory access subsystem and the L1 data cache to allow for selection of certain intermediate values to be stored in on-chip scratchpad memory as well as selecting the most appropriate tile size. In this way, we effectively decompose the graph in a way to fuse specific sets of nodes to associate their internal edges with on-chip buffers. Additionally, the tile size is optimized for each fused set of nodes. In this paper, we describe our performance models and approach for graph decomposition and tile size selection. The proposed performance models are accurate to within 2% on average, and the overall approach of graph optimization achieves an average speedup of 1.3 and allows for reduction of average DRAM utilization from 100% to as low as 15%.
A stochastic compact model for resistive switching devices is presented. The motivation is twofold: first, introducing variability in a natural way, and second, accounting for the discrete jumps of conductance observed during set and reset transitions. The model is based on an event generation rate, and it is an "on-the-fly" procedure because events are randomly generated as the simulation proceeds in time. For the generation of events, we assume a mixed non-homogeneous Poisson process. Before considering resistive switching, we deal with the generation of successive breakdown events in metalinsulator-semiconductor structures. This confirms the validity of the approach by comparing with experimental data in which discrete events are evident. To deal with resistive switching, we transform a previous compact model into a stochastic model. Comparison with experiments in TiN/Ti/HfO2/W devices show the validity of the approach. Current-voltage loops and potentiationdepression transients in pulsed experiments are captured with a single set of parameters. Moreover, the model is an adequate framework to deal with both cycle-to-cycle and device-to-device variability.
This paper is a continuation on my revolutionary theory of solving the pointwise fluid flow approximation model for time-varying queues. Thus, the long-standing simulative approach has now been replaced by an exact solution by using a constant ratio 𝛽 (Ismail's ratio) , offering an exact analytical solution. The stability dynamics of the time-varying 𝑀/𝐸 𝑘 /1 queueing system are then examined numerically in relation to time, 𝛽, and the queueing parameters.
This paper details an experiment utilizing ESP8266 modules as servers to wirelessly control diverse electrical appliances in home automation. The experiment showcased the modules' capability to respond to commands via a web interface on both mobile and desktop platforms or even tablets. While most of the experiment ran smoothly, occasional freezing and connectivity disruptions were observed. The abstract encapsulates the experiment's successes, discusses encountered challenges, and outlines a forward-looking perspective, including the integration of a custom PCB for enhanced system stability.
This paper presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least 3 rd order gradient effects. A new analysis leads to mathematical constraints on 1dimensional layouts that meet the required integer ratio and cancel 2 nd-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-dimensional layouts that cancel higher-order gradients. Importantly, our procedures can handle "dummy lanes" to ensure "routability". Furthermore, we discuss evaluation metrics that identify which of the multiple gradient canceling layout is best for any fixed rectangular grid and device application.
Design and verification of two-and three-pole differential bridged T-coils applicable to wideband and high-speed integrated circuits, broadband I/O terminations, capacitive loads, and ESD protection circuits are described. T-coil prototypes with 50-Ω terminations, designed for maximally flat amplitude (MFA) and envelope delay (MFED) responses, are characterized. Measured transimpedance bandwidth and group delay of the two-pole MFA design are 43.2GHz and 7±2ps across 45GHz, respectively. The bandwidth extension ratio (BWER) is 2.43x compared to an unpeaked R-C circuit. The three-pole MFED T-coil realizes a 2.2x BWER, with 23-GHz bandwidth and 12±2-ps group delay across 30GHz. Implemented in 22-nm FD-SOI CMOS technology, the T-coils occupy 224 x 215µm^2 .
In the past decade, focal muscle vibration (FMV) has gained wide attention in neurological rehabilitation for its non-invasive nature, ease-of-use, and minimal side effects. Disorders like stroke, cerebral palsy, and multiple sclerosis have shown rehabilitatory benefits from FMV. The effectiveness of FMV is closely tied to device parameters, particularly the frequency and location of vibration stimulation. Despite a variety of devices available on the consumer market and research community, there are often insufficient details for robust device evaluation and its purported effects, leading to performance variability among different devices under similar input conditions.This study aims to develop a well-characterized FMV device that is usable and comparable across various application domains. The research focuses on the development and validation of a custom-designed wearable vibration device designed to deliver precisely controlled muscle stimulation. The device utilizes an eccentric-rotating-mass (ERM) motor design and features a three-dimensional computer-aided design (CAD) model, a 3D printed casing, and a curved surface for enhanced comfort during muscle contact. Characterization of the device involved establishing the relationship between input (battery) voltages and output (vibration) frequencies. Accelerometers and a microcontroller were used for precise frequency determination. The subsequent design of an electronic circuit allowed for user-controlled frequency adjustments, complemented by a pressure sensor ensuring consistent pressure during device use. The study concludes with a well-characterized vibration device holding promise for applications in neuromuscular research, and rehabilitation, owing to its precision, versatility, and user-friendly design.
This work presents an analytical electro-thermal model for SMD-based printed circuit board (PCB) power converters. Temperature-dependent component losses are derived from analytical models and a 3-D thermal resistance network is employed to characterize the temperatures across components and PCB paths. Furthermore, the work explores the mechanical and thermal interaction within the PCB paths, concurrently analyzing semiconductor switches and the power inductor in synchronous commutation cell configurations. The proposed model undergoes evaluation with two different PCB layouts of a synchronous boost converter, operating at 350 kHz with 50 W and 75 W. Model-generated temperatures are compared with experimental measurements using a thermal imaging camera and with Finite Elements Analysis (FEA) in Ansys Icepak. The acquired results validate the accuracy of the proposed model.
We present an oscillator design based on stacked-FET for high power terahertz signal generation in CMOS technologies. This design addresses the challenges commonly encountered in conventional high-power oscillators. These challenges include low inductor quality factor (Q) associated with the use of large active devices, and the need for extensive chip area when combining multiple optimally-designed cells. Based on a Π-embedded oscillator architecture, we show that, with N-stacked FET, the optimal embedding inductor and load resistance increase approximately with N. This contrasts with the traditional size scaling approach, where L and R decreases unfavorably as the device size increases. We take advantage of this characteristic, by proposing a design methodology that simultaneously achieves high output power and optimal inductor Q. The concept is validated by a design example of a two-stacked Π-embedded oscillator operating at 180 GHz and fabricated in 45-nm CMOS SOI, delivering 11 dBm RF power from two losslessly combined oscillator cores. This design demonstrates the highest output power among CMOS oscillators at this frequency.