Abstract
The conventional computing platforms based on von-Neumann architecture
are highly space- and energy-intensive while handling the emerging
applications such as AI, ML, and big data. To overcome the von Neumann
bottleneck, compact and light-weight logic-inmemory implementations of
Boolean logic gates based on emerging non-volatile memory (e-NVM) such
as RRAMs, PCM, STT-MRAMs, etc., were proposed recently. However, these
e-NVMs not only exhibit significant temporal and spatial variability,
but their large-scale integration with CMOS process is also a
technological challenge. To overcome these issues with the emerging
non-volatile memories, Ferroelectric FETs based on CMOS-compatible doped
Hafnium oxide with the capability of large-scale CMOS integration in the
advanced logic nodes were proposed. Considering the high scalability and
CMOS-compatibility of the FeFETs, in this work, for the first time, we
propose a logic-inmemory implementation utilizing a single ferroelectric
fullydepleted-silicon-on-insulator (Fe-FDSOI) FET exploiting the unique
drain erase phenomenon. In our proposed logicin-memory implementation,
inputs are applied at the gate and drain terminals using a novel
input-to-voltage mapping scheme, and output is obtained as the current
flowing through the Fe-FDSOI FET. We utilize an experimentally
calibrated compact model of the ferroelectric capacitor connected to the
baseline industry standard BSIM-IMG compact model for the FDSOI
transistor for proof of concept demonstration. We also perform a
comprehensive analysis of the performance metrics of the proposed
logic-inmemory implementation. Our results indicate that we can realize
at least 10 Boolean logic gates with high energy and area-efficiency
utilizing the proposed scheme.