Modeling and Design of Cold-Start Charge Pumps for Photovoltaic Energy Harvesters

This article presents modeling and design optimization of switched-capacitor charge pumps for use as cold-start circuits in photovoltaic energy harvesters. For a successful cold-start from photovoltaic energy, a certain output voltage and current must be generated by the charge pump while jointly minimizing the required input voltage and current from the energy harvesting source. We model the operation of the cold-start charge pump including its oscillator, derive expressions for required input voltage and current based on output requirements, and demonstrate a Pareto-optimal design space that defines the tradeoff between the required input voltage and current to achieve cold-start. We then assess the impacts of process and temperature variation, and suggest a general design methodology for cold-start charge pump circuits. Finally, we validate models with measurements from a design fabricated in 55nm CMOS.


I. INTRODUCTION
S ELF-POWERED systems are enabling a proliferation of sensing applications in the Internet-of-Things (IoT) due to their limitless operating lifetime and low maintenance requirements.The ability for self-powered operation depends on both the power consumption of the system and the availability (type and amount) of ambient energy that can be harvested for consumption.Strong motivation to promote self-powered operation has therefore led to extreme power reduction in experimental [1] and commercialized [2] systems, as well as development of increasingly efficient energy-harvesting circuits that transduce photovoltaic, thermoelectric, piezoelectric, and RF energy into usable DC power for IoT sensor systems.
Among energy harvesting sources, photovoltaic (PV) is highly popular due to its widespread availability and high power density.A typical PV harvester circuit is shown in Fig 1 and consists of a main harvesting circuit and a cold-start circuit [1], [3], [4], [5].The main harvester implements a maximum power-point tracking (MPPT) algorithm with a flexible switched-capacitor architecture (variable frequency and conversion ratio) to extract as much power as possible during the steady state [6].Often, the circuits in the main harvester The authors are with Everactive Inc., Charlottesville, VA 22903 USA (e-mail: dst4b@virginia.edu).
Color versions of one or more figures in this article are available at https://doi.org/10.1109/TCSI.2023.3306308.
Digital Object Identifier 10.1109/TCSI.2023.3306308 will use the output voltage (V out ) as their supply since it provides more voltage overhead (for transistors to remain in saturation) and stability than the input voltage V pv .Due to the required supply voltage level and quiescent power of the main harvester, it is not ideal for enabling start-up from low input voltage and/or current conditions.Therefore, a minimal cold-start circuit consisting usually of just an auxiliary ring oscillator and a charge pump is responsible for accumulating enough energy at V out to allow the main harvester to boot up and take over operation.This transition is asserted by a power-on reset (POR) circuit that detects when the output voltage has charged to a safe level and turns off the coldstart circuit.In the cold-start circuit, both the oscillator and charge pump use the input V pv as their supply voltage.
In this utilization scenario, the design problem for such a cold start circuit is to deliver a specific output voltage and current adequate for cold-start while requiring the least input voltage and current possible.To create an effective design, all available primary knobs should be considered: oscillator frequency f osc , charge pump number of stages N , and charge pump capacitor size C pump .Additionally, the input voltage and current must be treated as a PV source rather than a fixed voltage.This is critical because the variable output voltage of the PV source affects the ring oscillator frequency as well as the maximum output current and voltage obtainable by the cold start circuit.For example, if the cold-start circuit draws too much current, V pv will droop and limit the output voltage.Conversely, limiting the current draw too much will prohibit cold-start at low input voltages due to inadequate output current.Process and temperature effects also must be considered, particularly due to the high variation susceptibility of the ring oscillator frequency, which in turn affects the current draw of the charge pump.
Currently, a wealth of charge pump optimization techniques exist to achieve a certain output voltage and current combination, however they assume a fixed input voltage which is not applicable in the case of PV harvesting [7], [8], [9].A more recent collection of works target operation with PV harvesting [10], [11], [12], [13], but the oscillator is not modeled and often treated as a system design input rather than part of the design which can be optimized.For example, [13] optimizes C pump and N but assumes both a fixed clock period and negligible oscillator current consumption.In [12], frequency is optimized for maximum power transfer, but again the oscillator is not included in the model, so its effect on the optimized design is not considered.While some PV harvesters use variation-robust relaxation oscillators with tunable frequencies [3], [14], they are less energy efficient and more complex than ring oscillators due to biasing requirements and therefore not ideal for cold-start operation.In summary, it is not clear from existing works how to jointly optimize a full cold-start circuit (including the ring oscillator) to achieve the desired output conditions while minimizing the input requirements.
This paper addresses the design of charge pumps specifically for application as cold-start circuits in PV energy harvesters.In section II, we model the cold start circuit including the PV input and the ring oscillator, and derive expressions for required input current and voltage to achieve cold start.In section III, we use the model to demonstrate a Pareto-optimal design space based on the charge pump design and the oscillator speed that balances the input voltage and current conditions required for cold-start while still ensuring that specific output voltage and current targets are met.We then assess how process and temperature variation affect the modeled Pareto-optimal performance, and then propose a general design methodology for jointly-optimized cold-start charge pump design.In section IV, we demonstrate a cold-start charge pump design with arbitrary design targets that was implemented used the proposed methodology.In Section V we present measurements of the cold-start charge pump in 55nm CMOS to validate the models and design methodology.Finally, in section VI we summarize the contributions and results.

II. COLD-START CIRCUIT MODEL
The full representative model of the cold-start circuit is shown in Fig. 1.The PV cell is modeled by an incident photocurrent I photo , which is proportional to ambient light intensity (lux), in parallel with a diode and shunt resistance R sh , followed by a series resistance R s before the output terminal V pv [15], [16].Note that these parameters, along with all following parameters, are summarized by Table II in the appendix.The output PV current I pv feeds directly into the cold-start circuit where it supplies the oscillator with I osc and the charge pump input with I in .Both of these currents are dynamic in nature.The charge pump output current I out is directed onto a storage capacitor C store .The charge pump represents a generic switched-capacitor design with ideal switches as discussed in [7], with N stages and pumping capacitor size C pump .Design techniques to boost charge pump efficiency such as boostrapping and gate drive boosting [9] are still represented well by this ideal model and are therefore generally independent from design problem and optimization results we present here.The fundamental equations describing the charge pump current are as follows [8]: And where the maximum steady-state output voltage (assuming no output load current) is where V in,ss is the steady-state charge pump input voltage.Since V pv is generally expected to be in the range of 0.2-0.6V(by design, based on solar cell characteristics), we can assume that the ring oscillator will be operating in or near the subthreshold region.In this region, the oscillator can be modeled with a simple exponential characteristic f osc = a osc e b osc V pv (4) where a osc represents the relative speed of the oscillator and b osc represents the supply voltage sensitivity.Once a osc and b osc are fitted, this expression takes the same form as the subthreshold current equation [17] which determines gate delay and therefore frequency in a ring oscillator in the subthreshold region.Measurement results are shown later in Fig. 16 to support this model.Note that (4) and (5) do not hold for very low V pv (<∼4kT/q) since it would yield inadequate noise margins for the gates in the ring oscillator to function correctly.5) is derived from the dynamic power expression P dyn = f ×C ×V 2 dd .The designer has some control over a osc , while b osc is mostly uncontrollable and will actually scale with a osc via the relationship where α and β are constants.This relationship is analytical based on the fact that the voltage sensitivity of a ring oscillator scales with its current speed, and will be demonstrated later with both simulation and measurement.Note that most ring oscillator topologies (such as differential, Schmitt triggerbased, leakage-based, etc.) can still be fit to this model.The linear region of I pv is expressed based on the series and shunt resistances by applying Ohm's law applied to Fig. 1, but for the purposes of simplicity can be represented as just the ideal Fig. 2. The solution for the PV cell output voltage V pv is the value which causes I cp to equal I pv .The real (computational) solution is shown as well as the approximated solution given by (9).Vertical alignment between these solutions indicated an ac curate approximation.
photocurrent source.We show next that this still results in reasonably accurate modeling solutions.
The value of V pv can be accurately approximated for a given I photo and V out by solving I photo = I cp , where I cp = I osc + I in as shown in Fig. 1 V pv = C pump V out (N + 1) where W 0 is the principal branch of the Lambert W function defined by W 0 [x] = y where the solution y satisfies ye y = x for y > −1 (principal branch) [18].Fig. 2 shows the characteristics of I photo , I pv , and I cp versus V pv for I photo = 5µA and V out = 0.7V .I cp increases exponentially with V pv due to the ring oscillator running faster and pulling more current through the charge pump as reflected by ( 1) and (4), as well as the exponentially increasing current consumption of the oscillator itself.The analytical solution for V pv from ( 9) is shown (based on simplifying I pv to I photo ), while the real solution for V pv occurs where I cp intersects the full I pv equation including the diodes and resistors.Due to the sharp exponential characteristic of I cp , the analytical solution for V pv falls close to the real solution, and is valid as long as V pv < V oc by around 50mV.Beyond this point, the real solution for V pv will plateau at V oc while (9) yields an result greater than V oc .In this case, V pv should just be assumed to equal V oc .

A. Transient Behavior
Fig. 3 demonstrates the transient operation of the coldstart circuit, where V out begins at 0V at time t = 0.The starting value for V pv at this point is calculated using (9) just as shown in Fig. 2. As time progresses, a chain effect occurs: first, charge is transferred to the output and V out rises, which alone would decrease I out due to the final term in (1).Fig. 3. Transient startup operation of cold-start circuit.Solid lines show V out , dashed lines show V pv .When a osc is tuned via adding stages to the ring oscillator, V pv,max and V out,max do not change (a).Tuning a osc via device threshold voltage allows V pv,max and V out,max to be modulated (b).V pv,max will plateau beneath V oc in either case if the oscillator is consuming enough current.
In fixed-frequency charge pumps, this would result in an RC-like output charging characteristic that can be simply modeled [7].However, in the present case with a PV input and ring oscillator, this decrease in I out (which translates to less I in ) allows V pv to rise due to a smaller current load.This higher V pv in turn causes the oscillator to speed up, which pulls more current through I in and I out , and so on.The final result is an approximately constant current source onto the output that is modeled as I out ≈ I photo /(N + 1).As V out is charging, V pv gradually increases.With an ideal oscillator (little or no current consumption), V pv would simply plateau at V oc , and V out would then plateau at (N + 1)V oc in accordance with (3).In reality, the oscillator steals current away from I cp and will continue to draw current even as the circuit reaches steady-state [V out → (N + 1)V pv ] once I in and I out drop to zero.The larger I osc is, the further V pv will plateau beneath V oc .The maximum value V pv,max is then determined by just the contention between I photo and I osc , obtained by solving I photo = I osc for V pv : Following this result, the maximum possible output voltage V out,max will simply be (N + 1)V pv,max .A V pv,max obtained from (10) greater than V oc indicates that I osc is relatively insignificant and that V pv,max will actually plateau at V oc .
Here, we make a critical observation on the approach for tuning the a osc knob, which affects both the power and frequency of the ring oscillator.Two approaches for tuning a osc are to change device thresholds (i.e., use low threshold voltage devices or high threshold voltage devices) or to add/subtract stages from the ring oscillator.If we decrease a osc by adding more stages to the ring oscillator, then C osc scales inversely.For example, doubling the number of ring oscillator stages will cut a osc in half, but double the total capacitance in C osc .This net effect cancels out in (10), leaving the limits for V pv,max and V out,max unchanged.Fig. 3(a) shows computationally-simulated waveforms using this design approach for a nominal frequency (a osc /1) as well as using 10x the number of stages (a osc /10) and 100x the number of stages (a osc /100).If we instead adjust a osc by using different threshold devices, then C osc remains the same and we can effectively scale the energy and frequency of the ring oscillator Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
together, which allows us to ensure by design that V pv,max and V out,max can reach the desired levels for a certain I photo .This result makes threshold voltage selection the preferred knob for a osc adjustment.

B. Constraining Output Current
In the analysis above, I out (and V pv ) has been implicit based on the values of I photo and V out .I out naturally tapers off as V out grows closer to V pv,max [as reflected by ( 2)], and falls off further due to I osc stealing an increasing amount of current as V pv and V out grow.If we define the desired output voltage and current to achieve cold-start as V target and I target respectively, then leaving I out implicit prevents any guarantee that it will be able to deliver I target when the output voltage is equal to V target .For example, if we design the charge pump with N =3, V target =0.95V, and we expect V pv,max =0.32 based on the oscillator characteristics and the available I photo , then V out,max =0.96V and we can assume I out will be quite low at V target since it V target so close to the maximum output voltage.This could be problematic depending on the requirements of the main harvester.Leakage in the main harvester (as well as any load circuits) can place requirements on I target , and if the main harvester creates an in-rush of current when it starts up, V out could droop too suddenly and introduce instability or brownout in the main harvester.To enable selection of I target , we constrain I out from (2) as The required V pv that will allow I out = I target and V out = V target to be achieved is found by solving (11) (with I out = I target ) for V pv , resulting in With I out and V pv now constrained, the required input I photo to enable cold start is now implicit.We define this required input photocurrent as I photo,req , which must deliver the total input charge pump current equal to I cp = I osc + I in .Using (1), (2), and (5) we have This can be fully expressed by expanding the above result as I photo,r eq = I target (N + 1) With ( 12) and ( 14), we now have the ability to design around both the input and output voltage and current based on the application needs.As long as I photo > I photo,r eq , V pv,r eq will  be generated (as long as the solar cell V oc > V pv,r eq ) and the desired outputs V target and I target will be generated.Based on other constraints and specifications in the system such as the startup current consumption of the main harvester, V target and I target can also be margined to ensure that a smooth handoff to the main harvester occurs.

III. DESIGN OPTIMIZATION
For a set of desired cold start output targets (I target and V target ), three primary design knobs exist as mentioned previously: oscillator speed a osc (via threshold voltage selection), charge pump number of stages N , and charge pump capacitor size C pump .In general, it is profitable to use a large C pump , and as a result it is common for existing design optimization techniques to use a fixed area constraint to avoid excessively large C pump .Since capacitance is proportional to area, it is helpful to evaluate the largest capacitance C max that can be fit in the available silicon area.Then, the knob C pump is implicitly set by C pump = C max /N .By sweeping the two remaining knobs, we obtain a Pareto-optimal design Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.
space demonstrated in Fig. 4. Curves are shown for different N by sweeping a osc , with b osc implicitly set by (6).This is performed both for a fixed C pump as well as for the area-constrained case where C pump is implicitly reduced as N is increased.For these results, we pick arbitrary design targets of I target = 1µA, V target = 0.7V , and C max = 15pF.The general trend is that lower N requires less photocurrent to cold-start, but in turn requires a higher V pv .For any N , an ideal a osc exists (a osc,opt ) at the Pareto-optimal point that balances I photo,req and V pv,req with respect to the ideal point represented by the asymptotes I target * (N + 1) (for I photo,req ) and V target /(N + 1) (for V pv,req ).Designing the oscillator slower than a osc,opt won't affect I photo,req , but it will raise V pv,req .Conversely, raising a osc above the Pareto-optimal point won't change V pv,req but will increase I photo,req .Closedform representations of Pareto-optimal solutions are often prohibitively complex, however we can reasonably estimate a osc,opt with where Note that this derivation makes use of (6) to express b osc in terms of a osc such that a single optimal value for a osc,opt may be obtained.An explanation for how this approximation is obtained is given in the Appendix.Table I shows the numerically-calculated values of a osc,opt versus N for a selection of V target and I target values.Again, a C max of 15pF is used here.In general, a osc,opt increases with higher I target , increases with higher N , and decreases with higher V target .As V target increases, low N cannot be used because a osc would need to be unrealistically low.For each of these a osc,opt values, since they are positioned at the Pareto-optimal point, it can be reasonably assumed that the associated I photo,req and V pv,req are equal to their asymptotic values, I target * (N + 1) and V target /(N + 1), respectively.For the design targets in this work of I target = 1µA and V target = 0.7V , N is chosen to be N = 2, yielding a numerically-computed a osc,opt of 69.1k while (15) predicts a value of 65.7k.For all values in the table, the error between numerically-computed a osc,opt and the value predicted by (15) averages out to slightly under a factor of 2x.This inaccuracy in (15) is generally negligible compared to the granularity of a osc available to designers (100-1000x), resulting in the same design selection despite the approximation error.

A. Process and Temperature Variation
Among the design knobs, a osc is the most susceptible to process and temperature variation.This is because the ring oscillator frequency (represented by a osc ) depends on transistor on-current, which scales strongly with temperature due to the temperature sensitivity of threshold voltage and charge carrier mobility [17].On-chip capacitors (C pump ) are generally robust to both process and temperature variation and N is not influenced by variation at all of any kind.Therefore, to analyze the impacts of variation on the charge pump operation, it is necessary to extract a osc and b osc across process and temperature corners.These two parameters alone, once extracted, encapsulate the majority of the impacts of variation on the overall design.To treat a osc as a design knob in this example, we create three ring oscillators.The first uses exclusively low threshold voltage (LVT) devices, the second uses exclusively standard threshold voltage (RVT) devices, and the third uses exclusively high threshold voltage (HVT) devices.All ring oscillators use the same design which will be shown later.Each design is simulated across process (TT,FF,SS,FS,SF) and temperature (−40C to 85C) corners by sweeping the ring oscillator supply voltage and curve-fitting the resulting frequency-vs-voltage characteristic to obtain a osc and b osc based on the relationship given by (4).The resulting parameters are shown in Fig. 5.As expected, the HVT design provides the lowest a osc values while the LVT design provides the highest a osc values, with the average difference between the two being about 3-4 orders of magnitude.Across process and temperature corners, a osc will vary significantly for any design.Specifically, since the ring oscillator operates in the subthreshold region, a osc increases exponentially with temperature since subthreshold current increases exponentially with temperature [17].This is not necessarily problematic, but it will affect where the design operates relative to the Pareto-optimal point.For the targeted value of a osc,opt = 69.1k in this work, the LVT design delivers the closest match on average.Values for b osc correlate well with a osc according to (6), with the highest levels of voltage sensitivity corresponding with the slowest oscillator speeds.For this work in 55nm CMOS, α = −1.2 and β = 26 when calibrated for all device types, corners, and temperatures.Parasitics have negligible impact on α and β.
The a osc and b osc values shown in Fig. 5 are used to compute I photo,req and V pv,req (for the same I target = 1µA, V target = 0.7V example as shown previously) to demonstrate how variation in a osc affects where the performance of the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Fig. 6.Resulting design performance of cold-start circuit using either low a osc (HVT devices, left) or high a osc (LVT devices, right) to implement the ring oscillator.Dashed lines show the theoretial model from Fig. 4. For any N , the process and temperature variation in a osc causes I photo,req and V pv,req to span a range of values, shown by the markers.In this example, an N=2 charge pump with LVT devices offers near-optimal performance.design falls within the Pareto-optimal design space.The computed results are shown in Fig. 6.Since the HVT oscillator yields the lowest a osc values well beneath the a osc,opt for any N, performance is skewed well beyond the Paretooptimal point, minimizing I photo,req but leading to a relatively high V pv,req .The lowest possible I photo,req across corners is achieved by the HVT oscillator via an N = 1 design.Since the LVT oscillator has a higher a osc than the HVT oscillator, the performance falls closer to the Pareto-optimal point.Still, for N > 2, the LVT a osc also falls below a osc,opt , so V pv,req skews above the Pareto-optimal point just like in the HVT version.For N = 1 however, the LVT a osc can vary both above and below the a osc,opt of 503, leading to performance that straddles the Pareto-optimal point.The downside in this case is that some corners will require substantially more photocurrent than the Pareto-optimal value.In fact, with the exception of a few corners, the N = 2 design requires less photocurrent than the N = 1 design when using LVT devices, confirming its selection as the best choice for balanced cold-start requirements.

B. General Design Methodology
Fig. 7 demonstrates the general design procedure to optimize operation based on desired design targets.Upon choosing the cold-start output requirements I target and V target , N should be chosen first based on the preferred range for I photo,req and V pv,req .Preferred ranges for I photo,req and V pv,req would be derived from the solar cell parameters, based on its V oc and physical area which determines how much I photo is generated from a specific amount of ambient light.Assuming that operation at the Pareto-optimal point will be targeted, I photo,req and V pv,req can be approximated by the asymptotic values of I target * (N +1) and V target /(N +1), respectively, for the purposes of choosing N .Pumping capacitance should be chosen by C pump = C max /N as discussed previously based on the maximum capacitance that can be fit in the available silicon area for the design.Finally, (15) can be used to estimate the desired oscillator characteristics to obtain optimized operation.As shown previously in Section II, a osc should be tuned by selecting different threshold voltages in the devices used in the oscillator, and the resulting a osc and b osc are extracted via simulation of the ring oscillator across design corners and compared to a osc,opt to determine how the performance  will skew beyond (higher I photo,req , or higher V pv,req ) the anticipated Pareto-optimal asymptotic values.More accurate estimates for I photo,req and V pv,req can now be obtained with ( 14) and ( 12) if desired.Depending on the results, iteration to another N value may be necessary based on desired performance.For the example design in this work with I target = 1µA and V target = 0.7V , it was desired to keep V pv,req below 0.5V and then to subsequently minimize I photo,req , so N = 1 was initially chosen.Extracting a osc and b osc revealed that N = 2 satisfied our requirements better across corners than the N = 1 design once the wide process and temperature spread in a osc was accounted for.Finally, optimizations to the charge pump architecture such as bootstrapping, switch sizing, etc., can be performed last after the values of the input/output voltage and current and operating frequency are known.

IV. IMPLEMENTATION
A traditional MOS-based charge pump design is used in this work, shown in Fig. 8, with integrated bootstrapping via 4-phase operation originally demonstrated in [19] and described in more detail by [7].In a standard MOS-based charge pump, charge is moved though pass transistors ("pass") while voltage is boosted by V pv at each stage by switching the pumping capacitors (C pump ).Without additional supporting circuitry, the overdrive voltage of the pass transistors drops further at each stage of the charge pump.In the 4-phase bootstrapped design, the additional clock phases combined with bootstrap transistor ("boot") and capacitor C boot allow a constant gate overdrive to be maintained at each stage for decreased R on and therefore increased efficiency.A bootstrapped output switch is also added to stabilize the output voltage and prevent reverse current when the 2nd stage is switched low (φ 1 = 0).As described earlier, N = 2 was chosen for the design with a C max ≈ 15pF, so a C pump of approximately 7pF was chosen.C boot is on the order of 100fF.Due to the expected voltage levels in our design, we use core low threshold voltage devices to reduce on-resistance, and each device is placed in its own p-well using a triple-well process with source tied to body to maintain a constant V bs .N-wells are tied to V out to prevent forward-biased junction diodes since V out is the highest voltage seen by the design during transient operation.

A. Oscillator
Fig. 9 shows the non-overlapping clock generator to drive the 4-phase bootstrapped charge pump.In a standalone non-overlapping clock generator, an external clock signal is required as an input at node clk_base to drive the generator.Upstream circuitry in Fig. 9, such as the self-clocking mechanism block and the POR signal NAND gate, would not exist in this case.This input clock signal would typically be implemented with an inverter-based ring oscillator, and in this case would be designed in accordance with the methodology discussed previously (low number of stages and small devices to reduce C osc , and pick threshold voltage of all devices to scale a osc ).However, this configuration does not create any feedback to maintain timing margin for the 4-phase generation -if the input frequency is too high, the clock phases will collapse.This would require very careful design of the timing delays in the non-overlapping element to ensure that the ring oscillator is always delivering a long enough clock period at clk_base to allow time for all the phases (φ 1−4 ) to switch.We improve on this issue by adding a self-clocking mechanism that combinationally drives the non-overlapping generator as soon as the 4 phases have settled to ensure efficient and predictable operation.The self-clocking mechanism is depicted in Fig. 9, and simply transitions the clk_base signal once the clock phases with the highest phase delay have settled (limited by φ 2 or φ 4 depending on the clock phase).In this way, the design operates just as a ring oscillator and is completely compatible with the ring oscillator models presented earlier, and all logic gates use the LVT devices as described earlier based on the selection of a osc .Relative timing margin between the clock phases can still be controlled by selecting the long and short ("long τ " and "short τ ") delay elements.In general, less transistors are desirable for a small C osc , so the short delay should as short as possible to maintain phase separation.The long delay can be chosen to ensure adequate separation between φ 1 and φ 3 at the fastest design corner.A good starting point is to make the long delay double the value of the short delay.Finally, a signal gate is added for the POR signal to instantly halt operation and eliminate dynamic power once POR is asserted and the main harvester takes over operation.If brownout occurs, the cold-start charge pump will instantly begin running again.In schematic simulation, C osc is approximately 750fF and increases by 1.2x (average across all corners) after layout extraction, and a osc drops by approximately 5x (average across all corners) after layout extraction.The correlation between b osc and a osc is relatively unaffected by parasitics, with α and β changing by 13% and 16%, respectively, when extracted from ideal schematic versus extracted layout.

B. Integration
The remaining implementation of the cold-start circuit is shown in Fig. 10.Once POR is asserted and the cold-start charge pump is disabled, the main harvester will charge V out to 2.5V.Therefore, it is necessary to disconnect the output voltage from the cold-start charge pump to eliminate reverse-current and to prevent any damage to the core-domain (1.2V maximum) devices used in the charge pump.To avoid loading the POR signal, a digital buffer is added to drive the signal to the gate of the PMOS output switch.Using V pv as the supply voltage of this buffer would limit the V sg of the PMOS output switch (during logic high when cutoff is desired) once V out is higher than V pv , resulting in high leakage through the switch once the cold start circuit is disabled.On the other hand, using V out as the sole buffer supply could cause unpredictable behavior when V out is low during the charging phase.To remedy this, a voltage selection circuit provides the maximum supply voltage possible (between V pv and V out ) to the buffer to ensure reliable operation during startup and Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.maintain high gate overdrive for low leakage in the off-state.Finally, a frequency divider and level converter are added to measure the ring oscillator frequency.
V. MEASUREMENTS Fig. 11 shows the die photo of a system-on-chip [2] fabricated in 55-nm CMOS containing the presented cold-start charge pump circuit.The design occupies a footprint of 520µm by 180µm, with a vast majority of the area being consumed by the C pump MIM-capacitors.The active area occupies 105µm by 90µm.

A. Transient Operation
Fig. 12 shows a transient measurement of the cold-start operation with POR assertion and handoff to the main harvester.V pv gradually increases as V out charges during cold-start which matches the expected transient behavior modeled by (9), and the linear charging characteristic of V out during cold-start indicates a constant current delivered from the charge pump output as expected.Once V out reaches V target , POR is asserted, the cold-start charge pump is disabled, and the main harvester continues to charge V out .When powered from a 24mm x 10mm solar cell, the cold-start circuit is capable of booting the main harvester from 10 lux (measured, TT die at 25C) corresponding to an approximate I photo of 2.7µA.Note that this effective I photo,req is slightly less than the target design value of 3−4µA because of system design margin added to the I target value of 1µA.In reality, the main harvester in the test chip successfully cold-starts at a V target and I target less than the 0.7V and 1µA values we  began with here.Note that this margin is uncoupled from the models and design methodology presented here, and is left to the discretion of the designer to be added to V target and I target .

B. Cold-Start Requirements and Model Validation
We measure the cold-start performance of the fabricated charge pump design by fixing V out to the V target value of 0.7V, sweeping the input voltage at V pv , and measuring both the input and output currents.V pv,req and I photo,req are identified by finding the input V pv at which I out =I target =1µA.This process is repeated for 5 dies at each corner: FF, FS, SF, SS, and TT, all taken at room temperature.Fig. 13 shows the average measured V pv,req and I photo,req for each corner with comparison to the modeled values [using (12) and ( 14)] and simulated values.V pv,req is predicted very accurately with measured performance matching modeled performance well across corners.Error between model and measurement averages at 4% here.I photo,req falls reasonably close to the modeled values, but a discrepancy exists due extra leakage in the design that was not included in the model.Error between model and measurement here averages to 13% across corners.This discrepancy is not present in the simulated values since all forms of leakage are captured in the full schematic simulation.The primary source of this error is in the gates that drive C pump , which are treated as ideal in the model, but in reality will see some shoot-through current as well as gate and subthreshold leakage due to their large W/L ratio.Naturally, Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.Illustration of modeled and measured performance within the Pareto-optimal design space.'x' markers show modeled performance based on simulation-extracted parameters, and square markers show measured dies (5 per corner).this discrepancy is most significant at fast corners and high temperatures.If desired, this leakage can be compensated by adding a term to (14) that is representative of the leakage in any corner/temperature combination, such as k 3 * I leak where I leak is the leakage of a transistor in any particular corner and k 3 is a fitting parameter that accounts for the total W/L of the transistors in the design that are being considered for leakage.
The modeled and simulated results are further compared to the fully-modeled Pareto-optimal design space in Fig. 14.
Here, the full Pareto-optimal model is created just as in Fig. 4 by sweeping a osc using the simulation-extracted α = −1.2 and β = 26, with b osc implicitly set by (6) and with C osc treated as a constant.The corner-specific modeled points shown by 'x' markers are calculated using the exact simulation-extracted values for a osc , b osc , and C osc .Slight deviations in these points from the Pareto-optimal model arise just from inaccuracies in approximating b osc using (6).

C. Oscillator Performance
The frequency of the LVT ring oscillator was measured versus V pv for 5 dies from each corner.Fig. 15 shows the measurement of a osc and b osc .After correlating b osc with a osc , α = −1.29 and β = 23.7 are obtained, which match simulated values well.Fig. 16 shows the measured frequency versus V pv , with the calibrated model from (4) shown.As V pv rises above  the subthreshold region, measured frequency tapers off due to transistor current leaving the exponential region and entering saturation.

D. Efficiency
The end-to-end efficiency of the cold-start charge pump circuit is measured at a fixed V out of 0.7V by sweeping the input voltage at V pv and measuring both the input and output currents.Results are shown in Fig. 17 as a function of both the output current (I out ) and input voltage (V pv ).Note that power efficiency is theoretically limited by η max = V out /[(N + 1) * V in ] where V in = V pv here, so the Authorized licensed use limited to the terms of the applicable license agreement with IEEE.Restrictions apply.relative power efficiency (compared to the theoretically ideal converter) is also shown.This relative efficiency is also equivalent to η r elative = [I out * (N + 1)]/I in , also sometimes referred to as current efficiency.These results show that power efficiency is implicitly maximized by the proposed design methodology, since peak efficiency is reached at I out = 1µA.At this point, the relative efficiency ranges from 75-85% across corners.Fig. 18 summarized the measurements and the final design point of the fabricated charge pump design.

VI. CONCLUSION
This paper presented an analytical model of a charge pump circuit driven by a ring oscillator operating from a solar cell.The model uniquely accounts for the power and frequency dynamics of the ring oscillator, and equations were derived to evaluate the required input voltage and current necessary from the solar cell to deliver a specific voltage and current combination to the output of the charge pump.We illustrate a Pareto-optimal design space that trades off between the required input voltage and current of the charge pump to achieve a set of desired output conditions, and show that the speed of the ring oscillator, chosen via threshold voltage selection, dictates where the final performance falls within that Pareto-optimal design space.An expression is created to evaluate the optimal oscillator speed for balanced Pareto-optimal performance, and a general design methodology is suggested to design an optimized charge pump.We implemented a charge pump design in 55-nm CMOS following the proposed design methodology and presented measurements that demonstrate an efficiency that averages 80% relative to a theoretically ideal charge pump circuit, and performance that validates the derived models with an accuracy of > 85%.

A. Summary of Variables
Table II summarizes the descriptions and values of the variables used in this work.Most terms represent parameters from the schematic or model, and a few remaining variables are inputs from the designer that pertain to the design optimization methodology.

B. Approximation of a osc,opt
As shown by Fig. 4, the two primary performance metrics being balanced (I photo,req and V pv,req ) form a Pareto-optimal design tradeoff based on the oscillator speed a osc .For any combination of design parameters (number of stages N , capacitor size C pump ), an ideal a osc exists (a osc,opt ) at the Pareto-optimal point that balances I and V pv,req with respect to the ideal point represented by the asymptotes I target * (N + 1) (for I photo,req ) and V target /(N + 1) (for V pv,req ).This ideal point is depicted in Fig. 14, and a osc,opt can be defined as the point on the Pareto-optimal curve with the shortest distance to the ideal point.Exact mathematical methods to calculate this point are cumbersome, and further complicated by the forms of the underlying equations for V pv,req and I photo,req in ( 12) and ( 14) respectively.From observation, it is clear that the Pareto-optimal point occurs at the "elbow" of the Pareto-optimal curve, where V pv,req begins to rapidly grow as a osc is decreased.Therefore, we can find an analytical for a osc,opt by identifying the range of a osc that causes this inflection in V pv,req .This point becomes more clear after analyzing the behavior of (12) as follows.First, V pv,req from ( 12) can be written as where the argument to the Lambert function x this case is First, we note that b osc has a relatively weak dependence on a osc as shown by measurement data in Fig. 15.Therefore, the inflection in V pv,req with changing a osc is caused mainly by the W 0 [x] term and its sensitivity to a osc .At increasingly high a osc , x will tend to 0, and since W 0 [0] = 0, this causes the second term in (18) to also tend to 0, resulting in V pv,req flattening out and converging to its asymptotic value V target /(N + 1).In this region, we can approximate W 0 [x] with the Taylor series expansion of the principal branch of the Lambert function at x = 0, which can be expressed as Taking a limited number of terms from (20) allows us to approximate (18) as: V pvr eq,appr ox = V target N + 1 where x remains the value in (19).Fig. 19 shows both ( 18) and ( 21), normalized to the ideal asymptote V target /(N + 1) where x = 0 and the Taylor series approximation holds.In this region, ( 18) and (21) match well.Conveniently, ( 18) and ( 21) diverge at the Pareto-optimal inflection point due to their similar shared sensitivity to a osc .19. Normalized values of V pv,req from both the full expression in (12) and the approximated expression in (21).Both expressions diverge from the asymptotic value (normalized as 1 on y-axis) at the Pareto-optimal point for a osc , creating an inflection that can be sensed at V pvr eq,appr = 1.This analytical solution for a osc,opt falls close the value.
Here, a osc (and therefore x) is close enough to a osc,opt that W 0 [x] = 0 grows in (18) to create the inflection point, while (21) diverges from (18) due to the Taylor series approximation at x 0 no longer holding.We can then a osc,opt using the simplified formula for V pv,req in (21) to locate its point of divergence.By inspecting (21) characteristic Fig. 19, it can be seen that the divergence from the Pareto-optimal inflection point occurs for values x >= 1 where the second term (21) transitions from positive to negative beings to sharply decrease V pvr eq,appr ox .We can then approximate a osc,opt as value a osc where this divergence occurs since it is conveniently always located near the Pareto-optimal inflection point: a osc,opt = a osc : x − x 2 b osc = 0 (22) The solution for x = 1 leads us to a osc,opt = a osc : a osc e k 1 (αlna osc +β) where k 1 and k 2 are given by ( 16) and (17).The solution for (23) is finally given by (15).

Manuscript received 14
March 2023; revised 20 July 2023 and 5 August 2023; accepted 9 August 2023.Date of publication 25 August 2023; date of current version 26 October 2023.This article was recommended by Associate Editor K. Moez.(Corresponding author: Daniel S. Truesdell.)

Fig. 1 .
Fig. 1.System diagram of photovoltaic enery harvester (top) and detailed schematic model of cold-start charge pump circuit running from a solar cell (bottom).

Fig. 4 .
Fig.4.Pareto-optimal design space for balancing the required input current I photo,req and voltage V pv,req to achieve cold-start given output specifications V target = 0.7V and I target = 1µA.Design variables are charge pump stages N and ring oscillator speed a osc .Solid lines show solutions for a fixed C pump , while dashed lines show solutions assuming C pump is adjusted based on N to maintain constant silicon area.

Fig. 5 .
Fig. 5. Simulated ring oscillator model parameters a osc (relative speed) and b osc (voltage sensitivity) extracted across process and temperature corners for three different threshold voltage selections (HVT,RVT,LVT).Parameter b osc can be correlated with a osc even across process and temperature variation.

Fig. 7 .
Fig. 7. Flow chart demonstration of the proposed general design methodology to optimize the performance of cold-start charge pumps based on specified output characteristics.

Fig. 8 .
Fig. 8. Schematic of the implemented cold-start charge pump circuit.A 2-stage 4-phase bootstrapped charge pump is used to generate the output voltage from V pv .

Fig. 9 .
Fig.9.Schematic of the self-clocked 4-phase clock generator that functions as the ring oscillator that drives the charge pump.

Fig. 10 .
Fig. 10.Supporting circuitry in the cold-start charge pump implementation.An output switch eliminates reverse-current once the cold-start circuit is disabled upon POR.A level shifter is implemented to measure the ring oscillator frequency.

Fig. 11 .
Fig. 11.Die photo of self-powered system-on-chip [2] fabricated in 55-nm CMOS including the cold-start charge pump circuit.

Fig. 12 .
Fig. 12.Transient measurement of cold-start from ambient light and subsequent regulation by main harvester with MPPT.

Fig. 13 .
Fig. 13.Modeled, simulated, and measured cold-start requirements V pv,req and I photo,req .Measured data is averaged from 5 dies per corner.

Fig. 14 .
Fig.14.Illustration of modeled and measured performance within the Pareto-optimal design space.'x' markers show modeled performance based on simulation-extracted parameters, and square markers show measured dies (5 per corner).

Fig. 15 .
Fig. 15.Measured ring oscillator characteristics for 5 dies per corner.Correlation between b osc and a osc is shown by dashed line.

Fig. 16 .
Fig. 16.Measured ring oscillator frequency versus V pv .V pv is the ring oscillator supply voltage.Modeled values from (4) are shown by dashed lines.Coefficients a osc and b osc from the modeled values are obtained from simulation results shown in Fig. 5.

Fig.
Fig. Measured end-to-end effiiciency of the cold-start charge pump.

Fig. 18 .
Fig. 18.Summary of design parameters and measured performance.Measurements are shown for all corners at 25 • C. Output at POR is specified as V out = 0.7V , I out = 1µA.
x = I target N b osc e − bosc V target N +1C pump a osc (N + 1) 2

TABLE I NUMERICALLY
-COMPUTED PARETO-OPTIMAL VALUES OF a osc VERSUS N FOR SEVERAL V target AND I target COMBINATIONS TO OPTIMIZE COLD-START PERFORMANCE