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High-Density Memristor-CMOS Ternary Logic Family
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  • Xiaoyuan Wang ,
  • Pengfei Zhou ,
  • Jason Eshraghian ,
  • Chih-Yang Lin ,
  • Herbert Ho-Ching Iu ,
  • Ting-Chang Chang ,
  • Sung-Mo Kang
Xiaoyuan Wang
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Pengfei Zhou
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Jason Eshraghian
University of Michigan

Corresponding Author:[email protected]

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Chih-Yang Lin
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Herbert Ho-Ching Iu
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Ting-Chang Chang
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Sung-Mo Kang
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This paper presents the first experimental demonstration
of a ternary memristor-CMOS logic family. We systematically
design, simulate and experimentally verify the primitive
logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.
Jan 2021Published in IEEE Transactions on Circuits and Systems I: Regular Papers volume 68 issue 1 on pages 264-274. 10.1109/TCSI.2020.3027693